Optimization of Power and Area in Digital Signal Processing using Approximate Multiplier
نویسندگان
چکیده
To reduce power utilization and area are some of the most important criteria for the fabrication of Digital Signal Processing and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. In most of the multiplication, the multiplier is an energyhungry component. To improve energy efficiency of multipliers, the choice of multiplier is very important. Here Wallace tree multiplier along with Carry Look ahead Adder (CLA) is used in order to achieve fast computation but CLA occupies more area. The structure of Carry SeLect adder (CSLA) is used to increase the speed and reducing the area in CSLA. This paper introduces a method that modifies the CLA using Binary to Excess one Converter (BEC) based CSLA. Experimental analysis illustrates that the proposed architecture achieve advantages in terms of speed, area and power consumption.
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